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找到约 10,000 项符合「VHDL」的源代码

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txt 将16进制转化为std_logic.txt

VHDL: Converting a Hexadecimal Value to a Standard Logic Vector This example shows how to convert a hexadecimal value to a std_logic_vector. It is shown in both VHDL '87 (IEEE Std 1076-1987) and
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www.eeworm.com/read/416784/11013213

rpt downclk.rpt

Project Informationd:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\downclk.rpt MAX+plus II Compiler Report File Version 10.12 09/21/2001 Compiled: 12/08/2003 13:16:03 Copyright (C) 1988-2001
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www.eeworm.com/read/416456/11024521

txt 说明.txt

CAGenerator.vdh为CA编码的vhdl源文件，CAGeneratorTest.do为相应的Modelsim仿真用宏文件 CLKIN为输入的10.23MHz的时钟 X1IN为输入的X1历元信号，用以复位电路 SWITCH为选择卫星号的信号 CAOUT为对应卫星产生的C/A码 CLK50为向数据产生器发送的50Hz时钟信号
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www.eeworm.com/read/470877/6901229

npl 7-segment.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT 7-segment DESIGN 7-segment DEVFAM spartan3 DEVFAMTIME 0 DEVICE xc3s200 DEVICETIME 0 DEVPKG ft256 DEVPKGTIME 0 DEVSPEED -4 DEVSPEEDTIME
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ref hdllib.ref

EN ex3 NULL F:/7-segment/ex3.vhdl sub00/vhpl00 AR ex3 behavioral F:/7-segment/ex3.vhdl sub00/vhpl01
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log coregen.log

# Xilinx CORE Generator 6.2.03i # User = FATEMAc4gb6 Initializing default project... Loading plug-ins... All runtime messages will be recorded in F:\7-segment\coregen.log # busformat=BusFormatAng
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transcript

# Reading E:/altera/72/modelsim_ae/tcl/vsim/pref.tcl # OpenFile "C:/Documents and Settings/chengle/Lb/QuartusII/VHDL/VHDL/my_eda(10)/m/m.vhd"
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www.eeworm.com/read/465190/7059421

rpt aa.rpt

Project Information f:\vhdl\dyy\aa.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 04/15/2009 16:15:34 Copyright (C) 1988-2002 Al
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www.eeworm.com/read/170130/7102921

udo vt.udo

-- ProjNav VHDL simulation template: vt.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/308401/7117961

npl clock.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT clock DESIGN clock DEVFAM spartan3 DEVFAMTIME 0 DEVICE xc3s200 DEVICETIME 0 DEVPKG ft256 DEVPKGTIME 0 DEVSPEED -4 DEVSPEEDTIME 0 DEVTO
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