7-segment.npl

来自「VHDL Design of BCD to 7-segment decoder 」· NPL 代码 · 共 27 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT 7-segment
DESIGN 7-segment
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ex3.vhdl
DEPASSOC ex3 ex3.ucf
[STATUS-ALL]
ex3.lsoFile=WARNINGS,1239619178
[STRATEGY-LIST]
Normal=True