代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
www.eeworm.com/read/174928/9568087
log coregen.log
# Xilinx CORE Generator 6.3i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in C:\Xilinx\ise_works\buzhidao\coregen.log
# busform
www.eeworm.com/read/174927/9568280
udo test.udo
-- ProjNav VHDL simulation template: test.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
www.eeworm.com/read/174927/9568309
gfl dpram2.gfl
# XST (Creating Lso File) :
dpram2.lso
# xst flow : RunXST
dpram2.syr
dpram2.prj
dpram2.sprj
dpram2.ana
dpram2.stx
dpram2.cmd_log
dpram2.ngc
dpram2.ngr
# Implmentation : Translate
__projn
www.eeworm.com/read/170129/9818111
npl lab2.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT lab2
DESIGN lab2
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLE
www.eeworm.com/read/366183/9825699
txt readme.txt
请注意:
第94例是SPARC芯片的源描述,在本书的光盘中没有给出其源描述
代码,有关该描述的框架请参考.
如果您需要有关SPARC的详细资料以及完整代码,请与北京理工大学
ASIC研究所联系.
联系方法:
电话:010-68912434
信函:北京理工大学ASIC研究所 刘明业 教授收
邮编:100081
www.eeworm.com/read/169299/9868452
cmd_log fdce.cmd_log
sch2vhdl -family xc9500 -flat -suppress -w fdce.sch fdce.vhf
www.eeworm.com/read/169299/9868958
cmd_log count4.cmd_log
xst -intstyle ise -ifn __projnav/count4.xst -ofn count4.syr
ngdbuild -dd _ngo -i -p xc9500 count4.ngc count4.ngd
cpldfit -p xc9572-10-TQ100 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew slow -in
www.eeworm.com/read/364988/9884008
qmsg pro3.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/168700/9901605
ref hdllib.ref
EN compact_divider NULL D:/FPGA/仿真/Divider_定点除法器/compact_divider.vhdl sub00/vhpl02
EN devider NULL D:/FPGA/仿真/Divider_定点除法器/devider.vhdl sub00/vhpl00
AR devider behavioral D:/FPGA/仿真/Divider_定点除法器/d
www.eeworm.com/read/168700/9901653
hb_cmds
-proj d:\fpga\仿真\divider
-t t_divider.tbw
-source devider.vhdl
-entity devider
-ipcport 1038