coregen.log

来自「这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleec」· LOG 代码 · 共 22 行

# Xilinx CORE Generator 6.3i
# User = Administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in C:\Xilinx\ise_works\buzhidao\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=C:\Xilinx\ise_works\buzhidao
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=C:\Xilinx\ise_works\buzhidao
SETPROJECT .
Set current Project to C:\Xilinx\ise_works\buzhidao
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1794
XIPCPJSENDCORES spartan3