代码搜索：VHDL

找到约 10,000 项符合「VHDL」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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udo test241.udo

-- ProjNav VHDL simulation template: TEST241.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/374512/9401381

udo test242.udo

-- ProjNav VHDL simulation template: TEST242.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/176855/9481983

udo tcpu.udo

-- ProjNav VHDL simulation template: tcpu.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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udo walu.udo

-- ProjNav VHDL simulation template: walu.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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udo tcpu1.udo

-- ProjNav VHDL simulation template: tcpu1.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/176855/9482235

udo wexe.udo

-- ProjNav VHDL simulation template: wexe.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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log coregen.log

# Xilinx CORE Generator 6.1.03i # User = Administrator Initializing default project... Loading plug-ins... All runtime messages will be recorded in I:\cpu1\coregen.log # busformat=BusFormatAngleB
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log coregen.log

# Xilinx CORE Generator 6.3i # User = huangl Initializing default project... Loading plug-ins... All runtime messages will be recorded in G:\资料\Spartan-3\S3Demo\coregen.log # busformat=BusFormatA
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stx sdrm.stx

Release 6.3i - xst G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to . CPU : 0.00 / 2.59 s | Elapsed : 0.00 / 3.00 s --> ==================================
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stx sdrm_t.stx

Release 6.3i - xst G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to . CPU : 0.00 / 2.74 s | Elapsed : 0.00 / 2.00 s --> ==================================
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