coregen.log

用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码

# Xilinx CORE Generator 6.3i
# User = huangl
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in G:\资料\Spartan-3\S3Demo\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=G:\资料\Spartan-3\S3Demo
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=G:\资料\Spartan-3\S3Demo
SETPROJECT .
Set current Project to G:\资料\Spartan-3\S3Demo
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1034
XIPCPJSENDCORES spartan3