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找到约 10,000 项符合「VHDL」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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log coregen.log

# Xilinx CORE Generator 6.2i # User = wukong Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\work\coreban\submusic\coregen.log NEWPROJECT . SETPRO
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npl subseg.npl

JDF G // Created by Project Navigator ver 1.0 PROJECT subseg DESIGN subseg DEVFAM spartan3 DEVFAMTIME 0 DEVICE xc3s400 DEVICETIME 1101950441 DEVPKG pq208 DEVPKGTIME 0 DEVSPEED -4 DEVSPEEDTI
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prm counter.prm

PROMGEN: Xilinx Prom Generator I.27 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o E:\vhdl\binarycounter\//counter -u 0 E:/vhdl/binarycounter/binarycounter.bi
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qmsg traffic.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
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makedist

rm -f ./doc/* ./src/myhdl/* ./src/vhdl/* turbo.tar.gz cp ../src/myhdl/*.py ./src/myhdl/ cp ../src/vhdl/*.vhd ./src/vhdl/ #cp ../src/vhdl/compile ./src/vhdl/ #cp ../src/vhdl/*.py ./src/vhdl/ #cp ../src
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rpt ex09.rpt

Project Information d:\vhdl_ex\ex09.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 10/29/2003 10:58:46 Copyright (C) 1988-2002 Al
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dat bookinfo.dat

[General Information] 书名=VHDL程序设计 作者=曾繁泰 陈美金 页数=401 SS号=10279563 出版日期=2000年8月第1版
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lst netlist.lst

F:\vhdl\fifos\fifo_exp1\fifo89.ngc 1197101644 OK
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xst chipio.xst

set -tmpdir temp set -xsthdpdir temp run -ifn chipIO.prj -ifmt VHDL -ofn chipIO -ofmt NGC -p xc2s100-6tq144 -ent chipIO -iobuf YES
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xst chipio.xst

set -tmpdir temp set -xsthdpdir temp run -ifn chipIO.prj -ifmt VHDL -ofn chipIO -ofmt NGC -p xc2s100-6tq144 -ent chipIO -iobuf YES
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