subseg.npl

来自「这是非常好的vhdl例子」· NPL 代码 · 共 27 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT subseg
DESIGN subseg
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s400
DEVICETIME 1101950441
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE top.vhd
DEPASSOC clock top.ucf
[STATUS-ALL]
clock.ngcFile=WARNINGS,1101950459
[STRATEGY-LIST]
Normal=True