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[Files List] c:\program files\aldec\active-vhdl\vlib\std\src\standard.vhd=S c:\my designs\countersure\src\VHDL code1.vhd=S

3 ~E count2 c:\my designs\countersure\src\VHDL code1.vhd 4 ~A behaviour c:\my designs\countersure\src\VHDL code1.vhd 9

Design: 9:39 PM, Tuesday, March 31, 2009 Design: Opening design "c:\my designs\mux41sure\mux41sure.adf" Design: Error: C:\My Designs\mux41sure\src\VHDL code6.vhd cannot be compiled. Compilation...

[Project] Current config=Generic VCS=0 modified=2 [Configurations] Generic=mux41sure [Files] /VHDL code6.vhd=4, 1 29995547 469056588, 0, , , ,

6 ~E mux41 c:\my designs\mux41sure\src\VHDL code6.vhd 2 ~A beh c:\my designs\mux41sure\src\VHDL code6.vhd 9 ~E test_bench c:\my designs\mux41sure\src\VHDL code6.vhd 35 ~A test_mux41 c:\my designs\mux4

Design: 9:50 PM, Tuesday, March 31, 2009 Design: Opening design "c:\my designs\synchronouscounter\synchronouscounter.adf" Design: Error: C:\My Designs\synchronouscounter\src\VHDL code8.vhd cannot be

Compilation... File: .\src\VHDL code8.vhd Compile Entity "counter" Compile Architecture "archi" of Entity "counter" Error: COMP96_0046:VHDL code8.vhd : (2, 276): Sequential statement expected

1 ~E counter c:\my designs\synchronouscounter\src\VHDL code8.vhd 2

MESSAGE "File: .\src\VHDL code8.vhd" MESSAGE "Compile Entity "counter"" MESSAGE "Compile Architecture "archi" of Entity "counter"" ERROR COMP96_0046: "Sequential statement expected." "c:\my desi

Design: 8:39 PM, Tuesday, March 31, 2009 Design: Opening design "c:\my designs\halfadder\halfadder.adf" Design: Error: C:\My Designs\halfadder\src\VHDL code6.vhd cannot be compiled. Compilation...