代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
www.eeworm.com/read/414111/11130368
zip blink_led_vhdl.zip
www.eeworm.com/read/413470/11154910
txt 曼彻斯特编码vhdl程序.txt
entity me is
port (rst,clk16x,wrn : in std_logic ;
din : in std_logic_vector (7 downto 0) ;
tbre : out std_logic ;
mdo : out std_logic
) ;
end me ;
architecture v1 of me is
signal clk1x :
www.eeworm.com/read/413323/11159451
txt myself_uart_vhdl.txt
总体设计思路:
1)预计实现效果:通过串口调试助手，由PC发送数据给小系统板，板子接收到的数据在数码管上即时显示
并且通过发送模块发送回PC，在串口调试助手上显示出来。
2)模块划分:六大模块,1:波特率发送模块(clock_tx);2:fpga_to_pc 发送模块 (uart_tx);3:采样时钟模块(uart_re);
4:pc_to_fpga接收模块(uart_re);5:数码 ...
www.eeworm.com/read/267559/11174613
prj fifo89_vhdl.prj
vhdl work "F:\vhdl\fifos\fifo_exp1\fifo_exp1.vhd"
www.eeworm.com/read/335284/12541717
doc vhdl课程设计.doc
www.eeworm.com/read/248071/12603611
h vl2vhdl.h
#ifndef VL2VHDL_H
#define VL2VHDL_H
#include
class VL2VHDL
{
public:
virtual void toVHDL(FILE *fp)=0;
};
#endif
www.eeworm.com/read/248071/12603647
tex v2vhdl.tex
\documentclass{article}
\usepackage{epsfig}
\renewcommand{\figurename}{Figura}
\renewcommand{\tablename}{Tabelul}
\title{Convertor Verilog VHDL}
\author{Corciovei Marilen Aretius,}
\date{25.05.2000}
\
www.eeworm.com/read/248071/12603653
aux v2vhdl.aux
www.eeworm.com/read/248071/12603654
doc v2vhdl.doc
www.eeworm.com/read/248071/12603670
ps v2vhdl.ps
%!PS-Adobe-2.0
%%Creator: dvips(k) 5.85 Copyright 1999 Radical Eye Software
%%Title: v2vhdl.dvi
%%Pages: 3
%%PageOrder: Ascend
%%BoundingBox: 0 0 596 842
%%EndComments
%DVIPSWebPage: (www.radicaleye.c