代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
www.eeworm.com/read/221649/14731001
rpt iis_vhdl.fit.rpt
Fitter report for IIS_VHDL
Fri Mar 30 16:10:04 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2.
www.eeworm.com/read/221082/14758377
txt vhdl2vl.txt
VHDL to Verilog RTL transformer
In 1.0 version ,
some functions restricted, as follows:
1: not all support "Generate" statement,totally not support "if .. Generate "
2: Comment in vhdl may have
www.eeworm.com/read/221082/14758392
dll vhdl2vl.dll
www.eeworm.com/read/219736/14866563
prj se_pa_vhdl.prj
www.eeworm.com/read/219731/14867422
prj time_going_vhdl.prj
www.eeworm.com/read/215328/15064677
txt vhdl control cuurent motor .txt
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
ENTITY dccount IS
port (
clk : IN STD_LOGIC;
www.eeworm.com/read/214547/15096985
rpt dds_vhdl.map.rpt
Analysis & Synthesis report for dds_vhdl
Sat Sep 03 15:18:50 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version
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; Table of Contents ;
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1. Lega
www.eeworm.com/read/214547/15096996
eqn dds_vhdl.fit.eqn
--S1_q_a[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_m9t:auto_generated|altsyncram_t5b2:altsyncram1|q_a[9] at M4K_X19_Y13
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1
www.eeworm.com/read/214547/15097012
summary dds_vhdl.map.summary
Flow Status : Successful - Sat Sep 03 15:18:50 2005
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : dds_vhdl
Top-level Entity Name : DDS_VHDL
Family : Cyclone
Device