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dds_vhdl.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC; --系统时钟
FWOR
dds_vhdl.fit.smsg
Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Extra Info:
dds_vhdl.fit.summary
Fitter Status : Successful - Wed Sep 10 11:58:49 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : DDS_VHDL
Top-level Entity Name : DDS_VHDL
Family : Cyclone
Devi
dds_vhdl.tan.summary
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Timing Analyzer Summary
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dds_vhdl.asm.rpt
Assembler report for DDS_VHDL
Wed Sep 10 11:58:57 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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; Table of Contents ;
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1. Lega
dds_vhdl.fit.rpt
Fitter report for DDS_VHDL
Wed Sep 10 11:58:49 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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; Table of Contents ;
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1. Legal N
dds_vhdl.flow.rpt
Flow report for DDS_VHDL
Wed Sep 10 11:58:59 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Not