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vhdl减法.txt
entity lcnt is
port(clk:in std_logic;
q:out std_logic);
end lcnt;
architecture art of lcnt is
signal count:std_logic(4 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' th
blowfish.vhdl
-- Copyright © 2007 Wesley J. Landaker
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as publis