blowfish.vhdl

blowfish vhdl version

-- Copyright © 2007 Wesley J. Landaker <[e-mail]>
-- 
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
-- 
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library common;

entity Blowfish is
  generic (
    param_KEY_WIDTH : natural := 448
    );
  port (

    -- Clock & Reset
    RST_I : in std_logic;
    CLK_I : in std_logic;

    -- Key FIFO Interface
    KEY_EN_I   : in  std_logic; --new_key 
    KEY_DATA_I : in  std_logic_vector(param_KEY_WIDTH-1 downto 0); --key
    KEY_FULL_O : out std_logic;

    -- Input Data FIFO Interface
    W_EN_I   : in  std_logic;   --new_data
    W_ENC_I  : in  std_logic;   --encrypt 
    W_DATA_I : in  std_logic_vector(63 downto 0); --data_in
    W_FULL_O : out std_logic;

    -- Output Data FIFO Interface
    R_EN_I    : in  std_logic;   --ready
    R_DATA_O  : out std_logic_vector(63 downto 0); --data_out
    R_EMPTY_O : out std_logic

    );
end entity;

architecture rtl of Blowfish is

  signal key_r_en    : std_logic;
  signal key_r_data  : std_logic_vector(447 downto 0);
  signal key_r_empty : std_logic;

  signal i_data_r_en    : std_logic;
  signal i_data_r_enc   : std_logic;
  signal i_data_r_data  : std_logic_vector(63 downto 0);
  signal i_data_r_empty : std_logic;

  signal o_data_w_en   : std_logic;
  signal o_data_w_full : std_logic;

  signal Pi_addr : std_logic_vector(9 downto 0);
  signal Pi_data : std_logic_vector(31 downto 0);

  signal P_enc      : std_logic;
  signal P_r_en     : std_logic;
  signal P_r_addr   : std_logic_vector(4 downto 0);
  signal P_r_data   : std_logic_vector(31 downto 0);
  signal p_w_en     : std_logic;
  signal p_w_addr   : std_logic_vector(4 downto 0);
  signal p_w_data_i : std_logic_vector(31 downto 0);

  signal S1_r_en     : std_logic;
  signal S1_r_addr   : std_logic_vector(7 downto 0);
  signal S1_r_data   : std_logic_vector(31 downto 0);
  signal S1_w_en     : std_logic;
  signal S1_w_addr   : std_logic_vector(7 downto 0);
  signal S1_w_data_i : std_logic_vector(31 downto 0);

  signal S2_r_en     : std_logic;
  signal S2_r_addr   : std_logic_vector(7 downto 0);
  signal S2_r_data   : std_logic_vector(31 downto 0);
  signal S2_w_en     : std_logic;
  signal S2_w_addr   : std_logic_vector(7 downto 0);
  signal S2_w_data_i : std_logic_vector(31 downto 0);

  signal S3_r_en     : std_logic;
  signal S3_r_addr   : std_logic_vector(7 downto 0);
  signal S3_r_data   : std_logic_vector(31 downto 0);
  signal S3_w_en     : std_logic;
  signal S3_w_addr   : std_logic_vector(7 downto 0);
  signal S3_w_data_i : std_logic_vector(31 downto 0);

  signal S4_r_en     : std_logic;
  signal S4_r_addr   : std_logic_vector(7 downto 0);
  signal S4_r_data   : std_logic_vector(31 downto 0);
  signal S4_w_en     : std_logic;
  signal S4_w_addr   : std_logic_vector(7 downto 0);
  signal S4_w_data_i : std_logic_vector(31 downto 0);

  signal cipher_en_i   : std_logic;
  signal cipher_data_i : std_logic_vector(63 downto 0);
  signal cipher_busy   : std_logic;
  signal cipher_en_o   : std_logic;
  signal cipher_data_o : std_logic_vector(63 downto 0);
  signal cipher_p_init : std_logic;
  
begin

  block_key : block is
    signal key_r_data_raw : std_logic_vector(KEY_DATA_I'range);
  begin

    u_key_FIFO : entity common.MiniFIFO
      generic map (
        param_DATA_WIDTH => param_KEY_WIDTH
        )
      port map (
        RST_I     => RST_I,
        CLK_I     => CLK_I,
        W_EN_I    => KEY_EN_I,
        W_DATA_I  => KEY_DATA_I,
        W_FULL_O  => KEY_FULL_O,
        R_EN_I    => key_r_en,
        R_DATA_O  => key_r_data_raw,
        R_EMPTY_O => key_r_empty
        );

    proc_key_r_data : process (key_r_data_raw) is
      variable j : natural;
    begin
      j := key_r_data_raw'high;
      for i in 447 downto 0 loop
        key_r_Data(i) <= key_r_data_raw(j);
        if j = 0 then
          j := key_r_data_raw'high;
        else
          j := j - 1;
        end if;
      end loop;
    end process;
    
  end block;

  u_i_data_FIFO : entity common.MiniFIFO
    generic map (
      param_DATA_WIDTH => 65
      )
    port map (
      RST_I                 => RST_I,
      CLK_I                 => CLK_I,
      W_EN_I                => W_EN_I,
      W_DATA_I(64)          => W_ENC_I,
      W_DATA_I(63 downto 0) => W_DATA_I,
      W_FULL_O              => W_FULL_O,
      R_EN_I                => i_data_r_en,
      R_DATA_O(64)          => i_data_r_enc,
      R_DATA_O(63 downto 0) => i_data_r_data,
      R_EMPTY_O             => i_data_r_empty
      );

  u_o_data_FIFO : entity common.MiniFIFO
    generic map (
      param_DATA_WIDTH => 64
      )
    port map (
      RST_I     => RST_I,
      CLK_I     => CLK_I,
      W_EN_I    => o_data_w_en,
      W_DATA_I  => cipher_data_o,
      W_FULL_O  => o_data_w_full,
      R_EN_I    => R_EN_I,
      R_DATA_O  => R_DATA_O,
      R_EMPTY_O => R_EMPTY_O
      );

  block_control : block is
    type state_t is (S_STARTUP, S_IDLE, S_CIPHER, S_KEY, S_KEY_PARRAY_INIT, S_KEY_SBOX_INIT,
                     S_KEY_PARRAY_CIPHER, S_KEY_PARRAY_WRITE_HIGH, S_KEY_PARRAY_WRITE_LOW,
                     S_KEY_SBOX_CIPHER, S_KEY_SBOX_WRITE_HIGH, S_KEY_SBOX_WRITE_LOW);
    signal state, next_state : state_t := S_IDLE;
    signal count, next_count : unsigned(9 downto 0);
    signal prev_P_enc        : std_logic;
  begin

    S1_w_addr <= std_logic_vector(count(7 downto 0));
    S2_w_addr <= std_logic_vector(count(7 downto 0));
    S3_w_addr <= std_logic_vector(count(7 downto 0));
    S4_w_addr <= std_logic_vector(count(7 downto 0));
    
    proc_next_state : process (P_enc, Pi_data, cipher_busy, cipher_data_o,
                               cipher_en_o, count, i_data_r_data,
                               i_data_r_empty, i_data_r_enc, key_r_data,
                               key_r_empty, next_count, o_data_w_full,
                               prev_P_enc, state) is
      subtype pcount_t is natural range 0 to 17;
      variable pcount : natural;
    begin

      key_r_en <= '0';

      i_data_r_en <= '0';
      o_data_w_en <= '0';

      Pi_addr <= std_logic_vector(next_count);

      P_enc      <= '1';
      p_w_en     <= '0';
      p_w_addr   <= std_logic_vector(count(4 downto 0));
      p_w_data_i <= (others => '-');

      S1_w_en     <= '0';
      S1_w_data_i <= Pi_data;

      S2_w_en     <= '0';
      S2_w_data_i <= Pi_data;

      S3_w_en     <= '0';
      S3_w_data_i <= Pi_data;

      S4_w_en     <= '0';
      S4_w_data_i <= Pi_data;

      cipher_en_i   <= '0';
      cipher_data_i <= i_data_r_data;
      cipher_p_init <= '0';

      next_state <= state;
      next_count <= count;

      case state is
        
        when S_IDLE =>
          P_enc <= i_data_r_enc;
          if prev_P_enc /= P_enc then
            cipher_p_init <= '1';
          elsif cipher_busy = '0' then