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VHDL 的代码
fixed_synth.vhdl
-- Synthesis test for the fixed point math package
-- This test is designed to be synthesizable and exercise much of the package.
-- Created for vhdl-200x by David Bishop (dbishop@vhdl.org)
-- -------
float_synth.vhdl
-------------------------------------------------------------------------------
-- Synthesis test for the floating point math package
-- This test is designed to be synthesizable and exercise much of
bmul32.vhdl
-- bmul32.vhdl parallel multiply 32 bit x 32 bit two's complement
-- the main components are bmul32, special Booth 32 x 32 -> 16 bit multiplier
-- badd32 32 bit specialized adder for Booth multiplie
vhdl_var.h
#ifndef VHDL_var_H
#define VHDL_var_H
#define VHDL_var_others 0
#define VHDL_var_integer 1
#define VHDL_var_std_logic 2
#define VHDL_var_std_logic_vector 3
#define STD_VHDL
vhdl_var.cpp
//////////////////////////////////////////////////////////////////
// Basic VHDL Variable Container
//
// Writer : Boris Kipnis
// Last Update : 5/5/2005
//
#include "VHDL_var.h"
VHDL_var::VHDL_
led_set.vhdl
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED_SET IS
PORT (clk: IN STD_LOGIC; -- clk in 4.096MHz
send_in: in STD_LOGIC;