led_set.vhdl

自定义编码的红外发射器

LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY  LED_SET  IS
PORT        (clk: IN STD_LOGIC;        --  clk in 4.096MHz
             send_in: in STD_LOGIC; 
             set_in: in std_logic_vector(1 downto 0);
             send_out: out std_logic_vector(6 downto 0) );
END  ENTITY LED_SET;
ARCHITECTURE archt of LED_set  IS

BEGIN
    process (clk,send_in)
      begin
      if clk'event and clk='1' then
       case set_in is
         when "00" => send_out(0) <= send_in ;
                      send_out(1) <= send_in ;
                      send_out(2) <= '0';
                      send_out(3) <= '0';           
                      send_out(4) <= '0';           
                      send_out(5) <= '0';           
                      send_out(6) <= '0';           


         when "01" => send_out(0) <= send_in ;
                      send_out(1) <= send_in ;
                      send_out(2) <= send_in ;
                      send_out(3) <= send_in ;           
                      send_out(4) <= '0';           
                      send_out(5) <= '0';           
                      send_out(6) <= '0'; 
         when "10" => send_out(0) <= send_in ;
                      send_out(1) <= send_in ;
                      send_out(2) <= send_in ;
                      send_out(3) <= send_in ;           
                      send_out(4) <= send_in ;           
                      send_out(5) <= '0';           
                      send_out(6) <= '0'; 
         when "11" => send_out(0) <= send_in ;
                      send_out(1) <= send_in ;
                      send_out(2) <= send_in ;
                      send_out(3) <= send_in ;           
                      send_out(4) <= send_in ;           
                      send_out(5) <= send_in ;           
                      send_out(6) <= send_in ;   
         when others=> null;
        end case;
      end if;
    end process;
   end archt;