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VHDL 的代码
frequency_counter.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (rst,clk : in std_logic;
carry_in : in std_logic;
c
cannon_vhdl.prj
work cannon.vhd
sync_vhdl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity sync_vhdl is
port(clk: in std_logic;
sh,b,t,ss: inout std_logic;
s: out std_logic);
end sync_vhdl;
architecture a of syn
wand_vhdl.vhd
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package res_pack is
function res_func(data : in bit_vector)return bit;
end;
package body res_pack is
function re
wand_vhdl.vhd
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package res_pack is
function res_func(data : in bit_vector)return bit;
end;
package body res_pack is
function re