sync_vhdl.vhd

产生复合同步信号波形

library ieee;
use ieee.std_logic_1164.all;

entity sync_vhdl is
   port(clk: in std_logic;
        sh,b,t,ss: inout std_logic;
        s: out std_logic);
end sync_vhdl;

architecture a of sync_vhdl is
signal c1: integer range 1 to 640;
signal c2: integer range 1 to 320;
signal cnt:  integer range 1 to 1250;

begin
 process(clk) 
   begin
     if clk'event and clk='1' then
       if c1=640 then
         c1<=1;
       else
         c1<=c1+1;
       end if;
     end if;
  end process;
 
  process(c1,clk)
    begin     
      if clk'event and clk='1' then   
        if c1>=1 and c1<=48 then
           sh<='0';
        else
           sh<='1';
        end if;
      end if;
  end process;

  process(clk)
    begin
      if clk'event and clk='1'then
        if c2=320 then
           c2<=1;
        else
           c2<=c2+1;
        end if;
      end if;
  end process;

  process(c2,clk)
    begin 
      if clk'event and clk='1'then
        if c2>=1 and c2<=24 then
           b<='0';
        else
           b<='1';
        end if;
      end if;
  end process;
 
  process(c2,clk)
    begin
      if clk'event and clk='1'then
        if c2>=1 and c2<=272 then
           t<='0';
        else
           t<='1';
        end if;
      end if;
  end process;

  process(b)
   begin 
    if b'event and b='0' then 
      if cnt=1250 then
         cnt<=1;
      else
         cnt<=cnt+1;
      end if;
     end if;
  end process;

  process(cnt)
    begin 
      if cnt>=2 and cnt<=6 then
         ss<=b;
      elsif cnt>=7 and cnt<=11 then
         ss<=t;
      elsif cnt>=12 and cnt<=16 then
         ss<=b;
      elsif cnt>=17 and cnt<=626 then
         ss<=sh;
      elsif cnt>=627 and cnt<=631 then
         ss<=b;
      elsif cnt>=632 and cnt<=636 then
         ss<=t;
      elsif cnt>=637 and cnt<=641 then
         ss<=b;
      else
         ss<=sh;
      end if;
   end process;
   
   process(clk)
    begin
      if clk'event and clk='1' then
         s<=ss;
      end if;
   end process;

 end a;