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63_vhdl.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_gcd_disp is
end t
56_vhdl.vhd
-- Author : yzf
-- Created On: Tue Dec 12 08:26:19 1995
-- Testbench for prefetch.prefetch
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_prefetch is
end t
lcd1602.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity char_ram is
port( address : in std_logic_vector(5 downto 0) ;
data : out std_logic_vector(7 downto 0)
);
lcd1602.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity char_ram is
port( address : in std_logic_vector(5 downto 0) ;
data : out std_logic_vector(7 downto 0)
);
wand_vhdl.vhd
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package res_pack is
function res_func(data : in bit_vector)return bit;
end;
package body res_pack is
function re
wand_vhdl.vhd
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package res_pack is
function res_func(data : in bit_vector)return bit;
end;
package body res_pack is
function re
mti_vhdl.do
#----------------------------------------------------------
# Model Technology VHDL compiler script for the book
# Digital Signal Processing with FPGAs (2.edition)
# Author-EMAIL: Uwe.Meyer-B
vhdl.fc2
#----------------------------------------------------------
# Synopsys FPGA Compiler II VHDL simulation script vhdl.fc2
# for the book: DSP with FPGAs (2. edition)
# Author-EMAIL: Uwe.Meyer-Baese@
ddc_counter.vhdl
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
ENTITY ddc_counter IS
PORT(
clk : IN std_logic;
ena : IN std_logic;
reset :
ddc_tb.vhdl
LIBRARY ieee ;
USE ieee.std_logic_arith.all ;
USE ieee.std_logic_1164.all ;
ENTITY ddc_tb IS
END ddc_tb ;
ARCHITECTURE ddc_tb_arch OF ddc_tb IS
SIGNAL q_out : std_logic_vector (15 down