ddc_counter.vhdl

vhdl硬件设计实现一个数字上变频器

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;

ENTITY ddc_counter IS
      PORT(
           clk    : IN   std_logic;
           ena    : IN   std_logic;
           reset  : IN   std_logic;
           output : OUT  std_logic_vector(1 DOWNTO 0)
           );
END ddc_counter;

ARCHITECTURE rtl OF ddc_counter IS
    SIGNAL con_2: std_logic_vector(1 DOWNTO 0);
    BEGIN 
     
        PROCESS(clk)
           BEGIN
             IF(reset='1') THEN
                con_2<="00";

                ELSIF(ena='1')THEN
                     IF (clk='1' AND clk'EVENT)THEN
                       IF(con_2="11") THEN
                         con_2<="00";
                       ELSE
                         con_2<=signed(con_2)+'1';
                        END IF;
                      END IF;
                  END IF;
              
          END PROCESS;
     output<=con_2;    
END rtl;