代码搜索结果
找到约 10,000 项符合
VHDL 的代码
enableandstart_vhdl.prj
work "C:\Documents and Settings\People\Desktop\VLSIASS2\Register.vhd"
work "C:\Documents and Settings\People\Desktop\VLSIASS2\Full_Adder.vhd"
work "C:\Documents and Settings\People\Desktop\VLSIASS2\
register_vhdl.prj
work "C:\Documents and Settings\People\Desktop\VLSIASS2\Register.vhd"
inverter_vhdl.prj
work "C:\Documents and Settings\People\Desktop\VLSIASS2\Inverter.vhd"
transposedformfirfiltercore vhdl.txt
TransposedFormFIRFilterCore
entity filter is
Port ( clk : in std_logic;
rst : in std_logic;
new_data : in std_logic_vector(15 downto 0);
valid : in std_logic_vector(15 downto 0);
kz2.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
jsq4.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
jsq5.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins