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VHDL 的代码
dds_vhdl.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
dds_vhdl.pin
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and a
秒表vhdl.txt
--------分---------------秒-------------毫秒------
---count6-count5---count4-count3---count2-count1---
---毫秒位count2-count1采用每10ms计数一次,计数100次即1s向高位count3进1
---秒位count4-count3每60s到向分进1
---本秒表最大计时为59分59秒
vhdl1.vhd
-- 2/3/4/10jishu
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count is
port (clk :in std_logic;
rst :in std_logic;
en :in std_logic;