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dds_vhdl.qpf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
dds_vhdl.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
dds_vhdl.hif
Version 4.1 Build 181 06/29/2004 SJ Full Version
31
OFF
OFF
OFF
OFF
0
# entity
ADDER32B
# architecture
A:behav
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_fi
dds_vhdl.pin
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and a
dds_vhdl.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLK : IN STD_LOGIC;
FWORD : IN S
textio_body.vhdl
-- Std.Textio package body. This file is part of GHDL.
-- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the t