代码搜索结果
找到约 10,000 项符合
VHDL 的代码
multi_vhdl.txt
--
--------------------------------------------------------------------------------/
-- DESCRIPTION : Signed mulitplier:
-- A (A) input width : 4
-- B (B) inpu
vhdl1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pll is
port ( clk:in std_logic;
div:out std_logic);
end;
architecture one of pll is
signal i:std_logi
vhdl-jishushizhong.txt
主程序：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity DLED is
port(
CLK1,CLK2: in STD_LOGIC;———————CLK1：时钟记数时钟，CLK2：扫描显示时钟
PUL
dds_vhdl.qws
[ProjectWorkspace]
ptn_Child1=Frames
ptn_Child2=Workmode
ptn_Child3=ActionPoints
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
pt
dds_vhdl.cdf
/* Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP1C3T144) Path("F:/A_matiral/DDS_1k/
dds_vhdl.fld
F:/matiral/DDS/db/DDS_VHDL.quartus_db
dds_vhdl
q
V1
dds_vhdl.done
Sat Sep 10 08:55:35 2005