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VHDL 的代码
dds_vhdl.vhd
--主程序
--程序名
library ieee;
use ieee.std_logic_1164.all;
entity frqload is
port(num:in std_logic_vector(3 downto 0);
q:out integer range 0 to 312);
end frqload;
architecture a of frqload
vhdl1.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RPN_Calc is
Port ( Clk : in std_logic;
Switches : in std_