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vhdl1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Vhdl1 IS
PORT (a,b,s:IN STD_LOGIC;
c:OUT STD_LOGIC);
END Vhdl1;
ARCHITECTURE choice OF Vhdl1
vhdl1.done
Sat Dec 29 00:45:31 2007
vhdl1.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
vhdl1.hif
Version 6.0 Build 178 04/27/2006 SJ Full Version
39
2097
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-
vhdl1.qpf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
vhdl1.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
vhdl1.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to