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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Vhdl2 IS PORT (d:IN STD_LOGIC_VECTOR (2 Downto 0); G1,G2A,G2B:IN STD_LOGIC; y:OUT STD_L

[ProjectWorkspace] ptn_Child1=Frames [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 [ProjectWorkspace.Frames.ChildFrames.Document-0]

Thu Jan 03 00:16:44 2008

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

Version 6.0 Build 178 04/27/2006 SJ Full Version 39 2097 OFF OFF OFF OFF OFF FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths -- -

-- Copyright (C) 1991-2006 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and a

/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Vhdl1 IS PORT (a,b,s:IN STD_LOGIC; c:OUT STD_LOGIC); END Vhdl1; ARCHITECTURE choice OF Vhdl1