vhdl2.vhd

程序提供了一种高效简单的38译码器的算法

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Vhdl2 IS
    PORT (d:IN STD_LOGIC_VECTOR (2 Downto 0);
          G1,G2A,G2B:IN STD_LOGIC;
          y:OUT STD_LOGIC_VECTOR (7 Downto 0));
END Vhdl2;
ARCHITECTURE decoder OF Vhdl2 IS
BEGIN
PROCESS (G1,G2A,G2B,d)
BEGIN
IF (G1 = '1' AND G2A = '0' AND G2B = '0' ) THEN
CASE d IS
WHEN "000" => Y<= "11111110" ;
WHEN "001" => Y<= "11111101" ;
WHEN "010" => Y<= "11111011" ;
WHEN "011" => Y<= "11110111" ;
WHEN "100" => Y<= "11101111" ;
WHEN "101" => Y<= "11011111" ;
WHEN "110" => Y<= "10111111" ;
WHEN "111" => Y<= "01111111" ;
END CASE;
ELSE
y <= "11111111";

END IF;
END PROCESS;
END decoder;