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vhdl1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xor_add is
port(clk:in std_logic;
din:in std_logic_vector(11 downto 0);
dout:out std_logic_vector(11 down
vhdl1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xor_add is
port(clk:in std_logic;
din:in std_logic_vector(11 downto 0);
dout:out std_logic_vector(11 down
dds_vhdl.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS_VHDL IS -- 顶层设计
PORT ( CLKK : IN STD_LOGIC;
FWORD
dds_vhdl.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
pt
dds_vhdl.cdf
/* Quartus II Version 4.1 Build 181 06/29/2004 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP1C6Q240) Path("D:/EDA_SOPC6_12/Chpt
dds_vhdl.done
Sat Sep 03 15:19:24 2005
dds_vhdl.qpf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth