代码搜索：TLC5510

找到约 86 项符合「TLC5510」的源代码

代码结果 86
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/181810/7154434

v tlc5510.v

module Tlc5510(data,Ctr,OE,Data_out); input Ctr; input[7:0] data; output OE; output[7:0] Data_out; assign Data_out=data; assign OE=Ctr; endmodule
·
www.eeworm.com/read/187637/8612723

rpt tlc5510.rpt

Project Information e:\cpld-fpga\tlc5510\tlc5510.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 11/11/2006 14:30:00 Copyright (C) 1988-2002 Al
·
www.eeworm.com/read/259066/11823868

hif tlc5510.hif

Version 5.0 Build 148 04/26/2005 SJ Full Version 32 1618 OFF OFF OFF OFF OFF FV_OFF VRSM_ON VHSM_ON 0 # entity TLC5510 # logic_option { AUTO_RAM_RECOGNITION ON } # case_insensitive
·
www.eeworm.com/read/338629/3314895

hif tlc5510.hif

Version 5.0 Build 148 04/26/2005 SJ Full Version 32 1618 OFF OFF OFF OFF OFF FV_OFF VRSM_ON VHSM_ON 0 # entity TLC5510 # logic_option { AUTO_RAM_RECOGNITION ON } # case_insensitive
·
www.eeworm.com/read/195919/8123054

vhd adsram.vhd

-- TLC5510 采样控制 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity adsram is port(rst : in std_logic; -- 复位 clk1 : in std_logic
·
www.eeworm.com/read/493788/6390671

vhd adsram.vhd

-- TLC5510 采样控制 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity adsram is port(rst : in std_logic; -- 复位 clk1 : in std_logic
·
www.eeworm.com/read/259066/11823929

vhd tlc5510.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TLC5510 IS PORT( CLK : IN STD_LOGIC; --采样控制Cctl_GP_LatchFlag输入 D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --8位AD数据 ADCLK : OUT STD_LOGIC;
·
www.eeworm.com/read/255033/12105109

vhd adsram.vhd

-- TLC5510 采样控制 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity adsram is port(rst : in std_logic; -- 复位 clk1 : in std_logic
·
www.eeworm.com/read/239356/13285218

vhd tlc5510.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY TLC5510 IS PORT(SYS_CLK:IN STD_LOGIC; DAT_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0); OE,CLK_OUT:OUT STD_LOGIC;
·
www.eeworm.com/read/187637/8612743

vhd tlc5510.vhd

--本模块为A/D转换器驱动模块，可根据具体需要调节时钟频率 --创建者：黄生专 --完成日期：2006.12.01 library ieee; use ieee.std_logic_1164.all; entity tlc5510 is port(clk:in std_logic; --系统时钟
·