adsram.vhd

信号采集与频谱分析电路

-- TLC5510 采样控制
library	IEEE;
use	IEEE.STD_LOGIC_1164.ALL;
use	IEEE.STD_LOGIC_ARITH.ALL;
use	IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adsram	is
	port(rst		: in	std_logic;	-- 复位
		clk1	: in	std_logic;	-- 50MHz Clock 输入；
		d		: in	std_logic_vector(7 downto 0);	-- 8位A/D数据
		q		: out	std_logic_vector(7 downto 0);	-- RAM 数据总线
		ramrden	: in	std_logic;
		ramrdck	: in	std_logic;
		rstaddr	: in	std_logic);
end adsram;
architecture testmod of adsram is
	type states is (st0,st1,st2);
	signal	current1,next1	: states;
	type adsstates is (sta0,sta1);
	signal	ads_state,next_ads_state : adsstates;
	signal	clkaddr	: std_logic;
	signal	addr	: std_logic_vector(9 downto 0);
	signal	clk0	: std_logic;
	signal	dis		: std_logic_vector(7 downto 0);
	signal	ioclk	: std_logic;
	signal	data	: std_logic_vector(7 downto 0);
	signal	address	: std_logic_vector(9 downto 0);
	signal	we		: std_logic;
component LPMRAM
		port(wren,inclock	: in	std_logic;	
			data	: in	std_logic_vector(7 downto 0);
			q		: out	std_logic_vector(7 downto 0);
			address	: in	std_logic_vector(9 downto 0));
	end component;
begin
ioclk <= clkaddr;
u1	: LPMRAM PORT MAP(data => data, address => address, wren => we,
					  inclock => ioclk,  q => q);
addres: process(clkaddr,rst,rstaddr)	-- RAM 地址控制
begin
	if(rst = '0' or rstaddr = '1') then	addr <= (others => '0');
	elsif clkaddr'event and clkaddr = '1' then	addr <= addr + 1;
	end if;
end process;
clkaddr <= 	clk0	when ramrden = '0' else
			ramrdck	when ramrden = '1' else
			ramrdck;
process(clk1)
begin
	if(clk1'event and clk1 = '1') then	address <= addr;
	end if;
end process;
process(clk1,rst)	-- SRAM写入控制状态机
begin
	if rst = '0' then	current1 <= st0;
	elsif clk1'event and clk1='1' then current1<=next1;--在时钟上升沿，转下一状态
	end if;
end process;
ram_wr_rd : process(current1,ramrden)
begin
	case current1 is
		when st0 => we <= '1'; clk0 <= '0';
					if(ramrden = '0') then	next1 <= st2;
					elsif(ramrden = '1') then next1 <= st1;
					else next1 <= st0;
					end if;
		when st1 => we <= '0'; clk0 <= '0';
					if(ramrden = '0') then	next1 <= st0;
					else next1 <= st1;	-- reading
					end if;
		when st2 => we <= '1'; clk0 <= '1';	next1 <= st0;		--writting
		when others => next1 <= st0;
	end case;
end process;
-- ###############################################################
       PROCESS (clk1) -- 此进程中，在LOCK的上升沿，将转换好的数据锁入
       BEGIN
        IF clk1'EVENT AND clk1='1' THEN	data <= D ;
        END IF;
       END PROCESS ; 
-- ###############################################################
end testmod;