代码搜索：Synthesizable
找到约 642 项符合「Synthesizable」的源代码
代码结果 642
www.eeworm.com/read/258631/11849620
doc synthesizable_fifo_verilog.doc
www.eeworm.com/read/234465/14111790
mht chapter16 synthesizable design.mht
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Subject: Chapter 16 Synthesizable Design
Date: Sun, 15 Feb 2004 15:49:15 +0800
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www.eeworm.com/read/382585/9018607
htm power scripts for i8051 synthesizable model.htm
Power Scripts for i8
www.eeworm.com/read/364127/9921613
v combi_ckt.v
// Synthesizable circuit (the "device-under-test")
module CombinationalCircuit (a,b,c,d,y);
input a,b,c,d;
output y;
reg y;
always @ (a or b or c or d)
y
www.eeworm.com/read/364127/9921623
v demo.v
// Synthesizable circuit (the "device-under-test")
module Demo (a,b);
input a;
output b;
assign b = ~a;
endmodule
www.eeworm.com/read/314969/13554830
pdf designing_multirate_filter_systems_in_fpgas_using_synthesizable_matlab.pdf
www.eeworm.com/read/284171/8957404
cpp add.cpp
/*
* TU Eindhoven
* Eindhoven, The Netherlands
*
* Name : add.cc
*
* Author : Sander Stuijk (sander@ics.ele.tue.nl)
*
* Date : July 23, 2002
*
* Fu
www.eeworm.com/read/284171/8957475
h add.h
/*
* TU Eindhoven
* Eindhoven, The Netherlands
*
* Name : add.h
*
* Author : Sander Stuijk (sander@ics.ele.tue.nl)
*
* Date : July 23, 2002
*
* Fun
www.eeworm.com/read/286434/8764351
pdf the fundamentals of efficient synthesizable finite state machine design using nc-verilog and buildgates.pdf
www.eeworm.com/read/233475/14149823
v syn_fifo.v
Synthesizable FIFO ModelThis example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH a