代码搜索：Synchronous
找到约 1,924 项符合「Synchronous」的源代码
代码结果 1,924
www.eeworm.com/read/151323/5684266
v or1200_spram_2048x32_bw.v
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM with byte write
www.eeworm.com/read/409540/11320153
v or1200_spram_1024x32_bw.v
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM with byte write
www.eeworm.com/read/409540/11320160
v or1200_spram_2048x32_bw.v
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM with byte write
www.eeworm.com/read/234533/4658638
v or1200_spram_1024x32_bw.v
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM with byte write
www.eeworm.com/read/234533/4658640
v or1200_spram_2048x32_bw.v
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM with byte write
www.eeworm.com/read/235392/14072803
v or1200_spram_1024x32_bw.v
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM with byte write
www.eeworm.com/read/235392/14072807
v or1200_spram_2048x32_bw.v
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM with byte write
www.eeworm.com/read/433021/8552033
vhd 带load_clr等功能的寄存器.vhd
--8-bit Register with Synchronous Load and Clear
The design entity shows the standard way of describing a register using a synchronous process, ie. a process containing a single wait statement which i
www.eeworm.com/read/5276/45848
v pci9054rdk-lite_cpld.v
//==============================================================
// 8/12/99
//
// Synchronous SRAM controller for PLX PCI 9054 mode C and J.
// 128K byte (32K x 32 bit) synchronous SRAM is u
www.eeworm.com/read/6885/104609
v pci9054rdk-lite_cpld.v
//==============================================================
// 8/12/99
//
// Synchronous SRAM controller for PLX PCI 9054 mode C and J.
// 128K byte (32K x 32 bit) synchronous SRAM is u