代码搜索：Synchronous
找到约 1,924 项符合「Synchronous」的源代码
代码结果 1,924
www.eeworm.com/read/8785/153077
v eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d
www.eeworm.com/read/10221/183809
v eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d
www.eeworm.com/read/17812/761153
v eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d
www.eeworm.com/read/17870/763221
v eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d
www.eeworm.com/read/17893/765639
v eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d
www.eeworm.com/read/18104/774865
v eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d
www.eeworm.com/read/18159/777934
v eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d
www.eeworm.com/read/18288/783075
v eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d
www.eeworm.com/read/18335/784558
vhd counter1.vhd
-- 8 bit up-counter with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity counter is
port (clk, reset: in b
www.eeworm.com/read/18360/785574
v eth_spram_256x32.v
`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// d