代码搜索：Synchronous
找到约 1,924 项符合「Synchronous」的源代码
代码结果 1,924
www.eeworm.com/read/18159/777825
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/18288/783259
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/18360/785758
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/18422/787489
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/18515/792222
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/18518/792855
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/18590/796362
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/32161/1032469
v fifo_2.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/32161/1032477
v fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/32675/1035585
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad