代码搜索：Synchronous
找到约 1,924 项符合「Synchronous」的源代码
代码结果 1,924
www.eeworm.com/read/102935/6228139
h isdn_ppp.h
/* $Id: isdn_ppp.h,v 1.17.6.1 2001/09/23 22:24:32 kai Exp $
*
* header for Linux ISDN subsystem, functions for synchronous PPP (linklevel).
*
* Copyright 1995,96 by Michael Hipp (Michael.Hipp@stud
www.eeworm.com/read/489686/6468796
v fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/486955/6521482
v generic_spram.v
`include "timescale.v"
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
`define VENDOR_FPGA
module generic_spram(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, ad
www.eeworm.com/read/406291/11445001
v fifo_2.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/401301/11559715
v fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/254980/12110175
v fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/339051/12264608
v fifo_2.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/339051/12264627
v fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/339051/12265663
v fifo_2.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
www.eeworm.com/read/339051/12265672
v fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15: