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#### START OF AREA REPORT #####[ Part: EP1S10FC780-5 (Altera) ---------------------------------------------------------------------- ######## Utilization report for Top level view: state

log_puts {@N|Using encoding styles selected by FSM Explorer.} log_puts {Data created on Fri Dec 16 18:27:37 2005} define_attribute {work.state2.verilog|i:CS[3:0]} syn_encoding {sequential}

source "C:/eda/synplicity/fpga_81/lib/altera/quartus_cons.tcl" syn_create_and_open_prj state2 source $::quartus(binpath)/prj_asd_import.tcl syn_create_and_open_csf state2 syn_handle_cons state2 s

set_global_assignment -name ROOT "|state2" -remove set_global_assignment -name FAMILY -remove set_global_assignment -section_id clk_setting -name DUTY_CYCLE "50.00" -remove set_instance_assignme

#Begin clock constraint define_clock -name {b:state2|clk} -period 1.000 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 0.500 -route 0.000 #End clock constraint

#Begin clock constraint define_clock -name {b:state1|clk} -period 1.961 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 0.981 -route 0.000 #End clock constraint

#Begin clock constraint define_clock -name {b:state2|clk} -period 2.746 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 1.373 -route 0.000 #End clock constraint

f "noname"; #file 0 f "noname"; #file 1 f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2 f "c:\prj\fsm_abc\state_default\state2_default.v"; #file 3 VNAME 'LUCENT.VLO.PRIM'; # view id 0 VNAM

@P: Worst Slack : -0.484 @P: state2_default|clk - Estimated Frequency : 309.6 MHz @P: state2_default|clk - Requested Frequency : 364.2 MHz @P: state2_default|clk - Estimated Period : 3.230 @P: