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(edif state2_default (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2005 12 16 16 56 10) (author "Synplicity, Inc.")

Selecting top level module state2_default @N:"C:\prj\FSM_abc\state_default\state2_default.v":2:7:2:20|Synthesizing module state2_default @N: CL201 :"C:\prj\FSM_abc\state_default\state2_default.v":

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Fri Dec 16 16:56:08 2005 Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synp

# # # # Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc. # Copyright 1994-2004 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Fri D

//Add a default state to make it more safe module state2_default ( nrst,clk, i1,i2, o1,o2, err ); input nrst,cl

Model { Name "mpc9state" Version 6.3 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelV

=pod =head1 NAME ERR_remove_state - free a thread's error queue =head1 SYNOPSIS #include void ERR_remove_state(unsigned long pid); =head1 DESCRIPTION ERR_remove_state() frees

=pod =head1 NAME SSL_state_string, SSL_state_string_long - get textual description of state of an SSL object =head1 SYNOPSIS #include const char *SSL_state_string(const SSL *ssl

#include #include #include #include #include "..\lib_amr\typedef.h" #include "..\lib_amr\enc_main.h" #include "..\include\mem.h" #include "..\include\pro

#include #include #include #include #include "..\lib_amr\typedef.h" #include "..\lib_amr\dec_main.h" #include "..\include\mem.h" #include "..\include\pro