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State Machine 的代码
tri_state.sim.rpt
Simulator report for tri_state
Thu Aug 02 16:25:24 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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1. Leg
tri_state.tan.rpt
Classic Timing Analyzer report for tri_state
Thu Aug 02 16:21:42 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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tri_state.asm.rpt
Assembler report for tri_state
Thu Aug 02 16:21:39 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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1. Leg
tri_state.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_state IS
PORT (control:IN STD_LOGIC;
in1:IN STD_LOGIC_VECTOR (8 DOWNTO 0);
q:INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
x: OUT ST
tri_state.flow.rpt
Flow report for tri_state
Thu Aug 02 16:21:42 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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1. Legal No
tri_state.map.summary
Analysis & Synthesis Status : Successful - Thu Aug 02 16:21:19 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : tri_state
Top-level Entity Name : tri_state
Family
tri_state.tan.summary
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Timing Analyzer Summary
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tri_state.fit.smsg
Extra Info: Performing register packing on registers with non-logic cell location assignments
Extra Info: Completed register packing on registers with non-logic cell location assignments
Extra Info:
tri_state.map.rpt
Analysis & Synthesis report for tri_state
Thu Aug 02 16:21:19 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
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; Table of Contents ;
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