📄 tri_state.vhd.bak
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_state IS
PORT (control:IN STD_LOGIC;
in1:IN STD_LOGIC_VECTOR (8 DOWNTO 0);
q:INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END tri_state;
ARCHITECTURE body_tri OF tri_state IS
BEGIN
PROCESS(control,q,in1)
BEGIN
IF(control='0') THEN x<=q;q<="ZZZZZZZZ";
ELSE q<=in1;x<="ZZZZZZZZ";
END IF;
END PROCESS;
END body_tri;
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