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State Machine 的代码
state_m2.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY state_m2 IS
PORT(clk, reset, nw : in std_logic;
sel: out std_logic_vector(1 down
assert_quiescent_state.vlib
// Accellera Standard V1.0 Open Verification Library (OVL).
// Accellera Copyright (c) 2005. All rights reserved.
`include "std_ovl_defines.h"
`module assert_quiescent_state (clk, reset_n, stat
rdopt_coding_state.h
/*!
***************************************************************************
* \file
* rdopt_coding_state.h
*
* \author
* Heiko Schwarz
*
* \date
* 17. April 2001
*
rdopt_coding_state.c
/*!
***************************************************************************
* \file rdopt_coding_state.c
*
* \brief
* Storing/restoring coding state for
* Rate-Distortion optim
rdopt_coding_state.h
/*!
***************************************************************************
* \file
* rdopt_coding_state.h
*
* \author
* Heiko Schwarz
*
* \date
* 17. April 2001
*
rdopt_coding_state.c
/*!
***************************************************************************
* \file rdopt_coding_state.c
*
* \brief
* Storing/restoring coding state for
* Rate-Distortion optim
ddr_3state.v
//
// Module: DDR_3state
//
// Description: Verilog instantiation template
// Double Data Rate Output with 3-state
//
//
// Device: VIRTEX-II Family
//-----------------------------------