ddr_3state.v

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//
// Module: 	DDR_3state
//
// Description: Verilog instantiation template
//		Double Data Rate Output with 3-state
//		
//
// Device: 	VIRTEX-II Family 
//---------------------------------------------------------------------

module DDR_3state (d0 , d1, data_out, en_0, en_1, clk, clk180, rst, set, ce);

input d0, d1, clk, clk180, rst, set, ce, en_0, en_1;

output data_out;
reg data_out;

wire q, q_tri;

//Synchronous Output DDR primitive instantiation

FDDRRSE U1  (   .D0(d0),
		.D1(d1),
		.C0(clk),
		.C1(clk180),
		.CE(ce),
		.R(rst),
		.S(set),
		.Q(q)
	    );


//Synchronous 3-State DDR primitive instantiation

FDDRRSE U2  (   .D0(en_0),
		.D1(en_1),
		.C0(clk),
		.C1(clk180),
		.CE(ce),
		.R(rst),
		.S(set),
		.Q(q_tri)
	    );

//3-State buffer description

always @ (q_tri or q)
  begin
	if (q_tri) 
	  data_out = 1'bz;
	else 
	  data_out = q;
  end

endmodule