代码搜索:State Machine

找到约 10,000 项符合「State Machine」的源代码

代码结果 10,000
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prf state2.prf

# # Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R. # # Period Constraints FREQUENCY PORT "clk" 364.2 MHz; # Output Constraints # Input Constraints BLOCK ASYNCPATHS;
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vqm state2.vqm

// // Written by Synplify // Synplify 8.1.0, Build 539R. // Fri Dec 16 18:27:37 2005 // // Source file index table: // Object locations will have the form : // file 0 "noname" // f
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xrf state2.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\stratix.v,
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srs state2.srs

# # # # Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc. # Copyright 1994-2004 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Fri D
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v state2.v

//2-paragraph method to describe FSM //Describe sequential state transition in 1 sequential always block //State transition conditions in the other combinational always block //Package state output
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prj state2.prj

#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file C:\prj\Example-6-1\FSM\state2\state2.prj #-- Written on Fri Dec 16 18:27:33 2005 #add_file options add_file -verilog "state2
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prj state1.prj

#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file C:\prj\FSM_abc\state1\state1.prj #-- Written on Fri Dec 16 14:50:01 2005 #add_file options add_file -verilog "C:/prj/FSM_abc
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prd state1.prd

#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file C:\prj\FSM_abc\state1\state1.prd #-- Written on Fri Dec 16 14:50:01 2005 # ### Watch Implementation type ### # watch_impl -a
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edn state1.edn

(edif state1 (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2005 12 16 15 1 10) (author "Synplicity, Inc.") (program
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msg state1.msg

@TM:1134715757 @W: BN132 :"":0:0:0:-1|Removing instance o2_22_u, because it is equivalent to instance N_79_i @W: BN132 :"":0:0:0:-1|Removing instance o1_23_u, because it is equivalent to instance