state2.prj

设计与验证verilog hdl

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\Example-6-1\FSM\state2\state2.prj
#-- Written on Fri Dec 16 18:27:33 2005


#add_file options
add_file -verilog "state2.v"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology STRATIX
set_option -part EP1S10
set_option -package FC780
set_option -speed_grade -5

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 1

#map options
set_option -frequency auto
set_option -run_prop_extract 0
set_option -fanout_limit 500
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -retiming 0
set_option -verification_mode 0
set_option -fixgatedclocks 0
set_option -no_sequential_opt 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#VIF options
set_option -write_vif 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/state2.vqm"

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1
impl -active "rev_1"