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State Machine 的代码
state_machine.v
module state_machine (devsel_l, trdy_l, stop_l, pci_ad_oe,
dts_oe, par_oe, bk_oe, pci_ad_en, hit_ba0_l, hit_ba1_l,
pci_frame_l, pci_idsel, pci_irdy_l, pci_ad, pci_cbe_l,
pci_clk, pci
state_machine.v
// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
state_machine.vhd
--------------------------------------
-- entity = state_machine --
-- version = 1.0 --
-- last update = 20/06/05 --
-- author = Jose Nunez -
state_machine.done
Fri Oct 20 16:36:40 2006
state_machine.pin
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
state_machine.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
state_machine.v
/*
简单的状态机，有8个状态,数码管输出当前状态的编号
state0--state1--state2--state3--state4--state5--state6-state7--state0
*/
module state_machine(clk,rst,c,en);
input clk,rst;
output[7:0] c;
reg[7:0] c;
output[7: