代码搜索：Specify
找到约 4,132 项符合「Specify」的源代码
代码结果 4,132
www.eeworm.com/read/137539/13314026
v delay.v
module delay(out,a,b,c);
output out;
input a,b,c;
and a1(n1,a,b);
or o1(out,c,n1);
specify
(a=>out)=2;
(b=>out)=3;
(c=>out)=1;
endspecify
endmodule
www.eeworm.com/read/136959/13352243
man getoptsl.man
FUNCTION: getopts_lite()
ABSTRACT: Command line argument processor. A subset of getopts() (also in
SNIPPETS), handles switches, options, literal data, file names
with or
www.eeworm.com/read/318986/13464781
v delay.v
module delay(out,a,b,c);
output out;
input a,b,c;
and a1(n1,a,b);
or o1(out,c,n1);
specify
(a=>out)=2;
(b=>out)=3;
(c=>out)=1;
endspecify
endmodule
www.eeworm.com/read/318888/13467782
cmd exp4.cmd
/* SPECIFY THE SYSTEM MEMORY MAP */
MEMORY
{
RAM (RWIX) : origin=0100h, length=00feffh /* Data Memory */
RAM1 (RWIX) : origin=010000h, length=000200h
RAM2 (RWIX) : origin=
www.eeworm.com/read/318888/13467789
cmd exp3.cmd
/* SPECIFY THE SYSTEM MEMORY MAP */
MEMORY
{
RAM (RWIX) : origin = 0100h, length = 01feffh /* Data Memory */
RAM2 (RWIX) : origin = 040100h, length = 040000h /* Program Memory */
www.eeworm.com/read/318888/13467801
cmd exp1.cmd
/* SPECIFY THE SYSTEM MEMORY MAP */
MEMORY
{
RAM (RWIX) : origin=0100h, length=01feffh /* Data Memory */
RAM2 (RWIX) : origin=040100h, length=040000h /* Program Memory */
ROM
www.eeworm.com/read/318888/13467836
cmd exp2.cmd
/* SPECIFY THE SYSTEM MEMORY MAP */
MEMORY
{
RAM (RWIX) : origin = 0100h, length = 01feffh /* Data Memory */
RAM2 (RWIX) : origin = 040100h, length = 040000h /* Program Memory */
www.eeworm.com/read/309649/13666919
man getoptsl.man
+++Date last modified: 05-Jul-1997
FUNCTION: getopts_lite()
ABSTRACT: Command line argument processor. A subset of getopts() (also in
SNIPPETS), handles switches, options, lit
www.eeworm.com/read/307658/13717922
v delay.v
module delay(out,a,b,c);
output out;
input a,b,c;
and a1(n1,a,b);
or o1(out,c,n1);
specify
(a=>out)=2;
(b=>out)=3;
(c=>out)=1;
endspecify
endmodule
www.eeworm.com/read/306749/13738853
v delay.v
module delay(out,a,b,c);
output out;
input a,b,c;
and a1(n1,a,b);
or o1(out,c,n1);
specify
(a=>out)=2;
(b=>out)=3;
(c=>out)=1;
endspecify
endmodule