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Serial 的代码
serial.do.bak
vcom F:/FPGA/feng_rs0/serial.vhd
vsim -t ps serial
add wave *
-- add wave tx1/*
add wave rx1/*
add wave fp/*
force rstn 0 0,1 100ps
force clk32 0 0,1 15.625 ps -r 31.250 ps
force rxd 1 0,0 10 ns,1
serial.fit.summary
Fitter Status : Successful - Thu Mar 05 15:45:52 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : serial
Top-level Entity Name : serial
Family : Cyclone
Device :
at91_serial.c
/*
* linux/drivers/char/at91_serial.c
*
* Driver for Atmel AT91RM9200 Serial ports
*
* Copyright (c) Rick Bronson
*
* Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
*
serial_con.c
#include "stdio.h"
#include "F2812reg.h"
#include "device.h"
Uint16 a,b;
#pragma DATA_SECTION(PieVectTable,"PieVectTable");
struct PIE_VECT_TABLE PieVectTable;
void initcpu()
{
a
.serial.o.cmd
cmd_arch/arm/mach-davinci/serial.o := arm_v5t_le-gcc -Wp,-MD,arch/arm/mach-davinci/.serial.o.d -nostdinc -iwithprefix include -D__KERNEL__ -Iinclude -Wall -Wstrict-prototypes -Wno-trigraphs -fno-stri
serial_pal.v
module serial_pal(clk,reset,en,in,out);
input clk,reset,en,in;
output[3:0] out;
reg[3:0] out;
always @(posedge clk)
begin
if(reset) out
serial2.v
module serial2(q,a,clk);
output q,a;
input clk;
reg q,a;
always @(posedge clk)
begin
a=~q;
q=~q;
end
endmodule
serial1.v
module serial1(q,a,clk);
output q,a;
input clk;
reg q,a;
always @(posedge clk)
begin
q=~q;
a=~q;
end
endmodule