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# Schematic : View VHDL Functional Model stopwatch.vhf stopwatch.cmd_log # Schematic : View VHDL Functional Model cnt60.vhf cnt60.cmd_log # XAW : View VHDL Source DCM1.vhd # Schematic : View V

SCHEMATIC START ; // created by map version G.23 on Tue May 08 22:45:13 2007 COMP "clk" LOCATE = SITE "P79" LEVEL 1; COMP "out" LOCATE = SITE "P102" LEVEL 1; SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.26 on Sat Apr 28 11:06:42 2007 NET "clk_BUFGP/IBUFG" BEL "clk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.23 on Thu Aug 16 15:37:02 2007 NET "CLK_BUFGP/IBUFG" BEL "CLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

# Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : PDCL (jhdparse) # Schematic : View Verilog Functional Model andnor2.vf # Schematic : View

SCHEMATIC START ; // created by map version G.38 on Tue Jun 26 13:01:19 2007 NET "CLK_IN_BUFGP/IBUFG" BEL "CLK_IN_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.38 on Tue Jun 26 12:51:21 2007 NET "SCLK_BUFGP/IBUFG" BEL "SCLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.38 on Tue Jun 26 13:05:41 2007 NET "SCLK_BUFGP/IBUFG" BEL "SCLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

SCHEMATIC START ; // created by map version G.38 on Tue Jun 26 13:03:36 2007 NET "SCLK_BUFGP/IBUFG" BEL "SCLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; SCHEMATIC END ;

(ExpressProject "Design1" (ProjectVersion "19981106") (ProjectType "PCB") (Folder "Design Resources" (Folder "Library") (NoModify) (File ".\design1.dsn" (Type "Schematic