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example_32bit_load.vhd
-- VHDL Model Created from SCS Schematic example_32bit_load.sch
-- Aug 15, 2003 13:22
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
example_32bit_load.v
/* Verilog Model Created from SCS Schematic example_32bit_load.sch
Aug 15, 2003 13:22 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
example_4bit_load.v
/* Verilog Model Created from SCS Schematic example_4bit_load.sch
Aug 15, 2003 10:23 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOGI
example_4bit_load.vhd
-- VHDL Model Created from SCS Schematic example_4bit_load.sch
-- Aug 15, 2003 10:23
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.al
example_4bit_load.vh
/* Verilog Header Created from SCS Schematic example_4bit_load.sch
Aug 15, 2003 10:23 */
module example_4bit_load( clear_in , clk_in, data, enable_in, load_in, count_out );
input clear_in,
example_en_32bit_s.v
/* Verilog Model Created from SCS Schematic example_en_32bit_s.sch
Aug 14, 2003 16:39 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
example_en_32bit_s.vhd
-- VHDL Model Created from SCS Schematic example_en_32bit_s.sch
-- Aug 14, 2003 16:39
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
example_en_32bit_s.vh
/* Verilog Header Created from SCS Schematic example_en_32bit_s.sch
Aug 14, 2003 16:38 */
module example_en_32bit_s( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
out
example_en_16bit_s.vq
`timescale 1ps / 1ps
/* Verilog Header Created from SCS Schematic example_en_16bit_s.sch
Aug 14, 2003 12:15 */
module example_en_16bit_s( clear_in , clk_in, enable_in, count_out );
input
example_en_16bit_s.v
/* Verilog Model Created from SCS Schematic example_en_16bit_s.sch
Aug 14, 2003 12:15 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG