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<TITLE> LOW-LEVEL DESIGN ENTRY</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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LOW-LEVEL <BR>
DESIGN ENTRY</H1>
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The purpose of <SPAN CLASS="Definition">
design entry</SPAN>
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is to describe a microelectronic system to a set of <A NAME="marker=2359">
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<SPAN CLASS="Definition">
electronic-design automation</SPAN>
(<A NAME="marker=2361">
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<SPAN CLASS="Definition">
EDA</SPAN>
) tools. Electronic systems used to be, and many still are, constructed from off-the-shelf components, such as TTL ICs. Design entry for these systems now usually consists of drawing a picture, a <A NAME="marker=2366">
</A>
<SPAN CLASS="Definition">
schematic</SPAN>
. The schematic shows how all the components are connected together, the <A NAME="marker=2369">
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<SPAN CLASS="Definition">
connectivity</SPAN>
of an ASIC. This type of design-entry process is called <A NAME="marker=2371">
</A>
<SPAN CLASS="Definition">
schematic entry</SPAN>
, or <A NAME="marker=2373">
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<SPAN CLASS="Definition">
schematic capture</SPAN>
. A circuit schematic describes an ASIC in the same way an architect’s plan describes a building.</P>
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The circuit schematic is a picture, an easy format for us to understand and use, but computers need to work with an ASCII or binary version of the schematic that we call a <A NAME="marker=24159">
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netlist</SPAN>
. The output of a schematic-entry tool is thus a netlist file that contains a description of all the components in a design and their interconnections.</P>
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Not all the design information may be conveyed in a circuit schematic or netlist, because not all of the functions of an ASIC are described by the connectivity information. For example, suppose we use a programmable ASIC for some random logic functions. Part of the ASIC might be designed using a text language. In this case design entry also includes writing the code. What if an ASIC in our system contains a programmable memory (PROM)? Is the PROM microcode, the '1's and '0's, part of design entry? The operation of our system is certainly dependent on the correct programming of the PROM. So perhaps the PROM code ought to be considered part of design entry. On the other hand nobody would consider the operating-system code that is loaded into a RAM on an ASIC to be a part of design entry. Obviously, then, there are several different forms of design entry. In each case it is important to make sure that you have completely specified the system—not only so that it can be correctly constructed, but so that someone else can understand how the system is put together. Design entry is thus an important part of <A NAME="marker=2394">
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<SPAN CLASS="Definition">
documentation</SPAN>
.</P>
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Until recently most ASIC design entry used schematic entry. As ASICs have become more complex, other design-entry methods are becoming common. Alternative design-entry methods can use graphical methods, such as a schematic, or text files, such as a programming language. Using a <A NAME="marker=2400">
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hardware description language </SPAN>
(<A NAME="marker=2403">
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<SPAN CLASS="Definition">
HDL</SPAN>
) for design entry allows us to generate netlists directly using <A NAME="marker=2405">
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logic synthesis</SPAN>
. We will concentrate on <A NAME="marker=2410">
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<SPAN CLASS="Definition">
low-level design-entry </SPAN>
methods together with their advantages and disadvantages in this chapter. </P>
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<H1 CLASS="Heading1TOC">
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9.1 Schematic Entry</A>
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9.2 Low-Level Design Languages</A>
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<A HREF="CH09.3.htm#pgfId=3353" CLASS="Hypertext">
9.3 PLA Tools</A>
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<A HREF="CH09.4.htm#pgfId=11261" CLASS="Hypertext">
9.4 EDIF</A>
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<A HREF="CH09.5.htm#pgfId=4672" CLASS="Hypertext">
9.5 CFI Design Representation</A>
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9.6 Summary</A>
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9.7 Problems</A>
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9.8 Bibliography</A>
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<A HREF="CH09.9.htm#pgfId=28736" CLASS="Hypertext">
9.9 References</A>
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<HR><P>[ <A HREF="../../ASICs.htm#anchor749424">Chapter Index</A> ] [ <A HREF="CH09.1.htm">Next page</A> ]</P></BODY>
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